1. Field of the Invention
The present invention relates to a shift register, and more particularly, a shift register pulling control signals according to display mode.
2. Description of the Prior Art
FIG. 1 illustrates operation waveforms of a driving control signal Q(n) and gate-terminal signal signals G(n) to G(n+7) in a three-dimensional (3D) display mode according to the prior art. FIG. 2 illustrates operation waveforms of the driving control signal Q(n) and the gate-terminal signal signals G(n) to G(n+7) in a two-dimensional (2D) display mode according to the prior art.
According to FIG. 1, in the 3D display mode, the gate-terminal signals G(n) and G(n+1) are in phase at edges of pulses, the gate-terminal signals G(n+2) and G(n+3) are in phase, the gate-terminal signals G(n+4) and G(n+5) are in phase, and the gate-terminal signals G(n+6) and G(n+7) are in phase. The rising edges of the gate-terminal signals G(n+1), G(n+3), G(n+5) and G(n+7) are separated by 0.5 pulse-widths successively, so the rising edge of the gate-terminal signal G(n+6) is later than the falling edge of the gate-terminal signal G(n) by a 0.5 pulse-width. In a shift register of the prior art, the first driving control signal Q(n) is pulled up by charging a capacitor of a pull-up circuit when the gate-terminal signal G(n) rises, and the first driving control signal Q(n) is pulled down by a pull-down circuit controlled by the gate-terminal signal G(n+6) when the gate-terminal signal G(n+6) rises. Therefore, as shown in FIG. 1, the first driving control signal Q(n) rises 0.5 pulse-width before the pulse of the gate-terminal signal G(n) and falls 0.5 pulse-width after the pulse of the gate-terminal signal G(n) in the 3D display mode. The said pulse-width is a pulse-width of a clock waveform.
According to FIG. 2, in the 2D display mode, The rising edges of the gate-terminal signals G(n) to G(n+7) are separated by one pulse-width successively, that is to say, the falling edge of the gate-terminal signal G(n) is in phase with the rising edge of the gate-terminal signal G(n+1), the falling edge of the gate-terminal signal G(n+1) is in phase with the rising edge of the gate-terminal signal G(n+2), . . . and the falling edge of the gate-terminal signal G(n+6) is in phase with the rising edge of the gate-terminal signal G(n+7). As described above, in a shift register of the prior art, the first driving control signal Q(n) is pulled up by charging a capacitor of a pull-up circuit when the gate-terminal signal G(n) rises, and the first driving control signal Q(n) is pulled down by a pull-down circuit controlled by the gate-terminal signal G(n+6) when the gate-terminal signal G(n+6) rises. Therefore, as shown in FIG. 2, the first driving control signal Q(n) rises two pulse-widths before the pulse of the gate-terminal signal G(n) and falls five pulse-widths after the pulse of the gate-terminal signal G(n) in the 2D display mode.
As illustrated by FIG. 2, in the 2D display duration, the driving control signal Q(n) is of a high floating state in the duration t1. The five pulse-width duration of the high floating state is overlong and keeps the pull-up circuit turned on, so the gate-terminal signals are easily interfered by noise, and pixels may be turned on at wrong time points to cause abnormal display. In addition, since a stabilizing circuit is still turned off, external noise may likely cause the shift register to operate incorrectly.